Temperature on the IBM Power Grid Benchmark Examples
- IBM has placed a set of SPICE-format power grid example circuits here.
- The power grids are based on real designs and come with current sources at the substrate level (cells?) and voltage sources at the top level (bumps?).
- Power grid sizes vary from 30638 nodes (ibmpg1) to 1670494 nodes (ibmpg6).
- TDA has converted several power grids to IEEE481 standard parasitic extraction format (SPEF) by assuming a hypothetical metal interconnect stack to provide resistor width and thickness and thermal coupling to substrate.
- Ibmpg5 has a single VSS net and four VDD nets, each covering one quadrant of the chip, so this design was chosen to compute Ember™'s scaling with number of nodes. Nets from ibmpg4 and ibmpg6 are included for comparison.
- For details of the ibmpg5 design, see Scaling.
- Temperature colour scale: 0.25 < ∆T < 6.0 C. For a clearer impression of the lower temperature range, see 3-D Substrate Temperature.

Ember™ temperatures vs. implied current density rule temperatures
- Foundry rms current density rules are intended to protect interconnect from high temperatures due to Joule self-heating without the need for a detailed temperature simulation.
- Rms current density rules are equivalent to the T∞ term in Ember™'s expression for temperature T(x).
- The benefits of using rms current density rules are:
- easy to do
- (that's the only benefit)
- Ember™ includes topology effects on temperature that are not addressed by the density rules:
- finite metal segment length
- thermal conduction between layers and down to the substrate through vias and contacts
- thermal injection from vias
- thermal coupling to locally variable substrate temperature
- thermal coupling between nets (where specified, e.g. by extracting couping capacitance)
- These topology effect completely alter the temperature predictions of the current density rule (Tinf), resulting in Ember™ maximum resistor temperature predictions (Tmax). See the graph below.


